Exemplary embodiments of the present invention relate to semiconductor fabrication technology, and more particularly, to a gate pattern of a semiconductor device and a method for fabricating the same.
Examples of conventional processes for forming a gate pattern of a semiconductor device are as follows.
FIGS. 1A and 1B are cross-sectional views illustrating processes of a conventional method for fabricating a gate pattern of a semiconductor device.
As shown in FIG. 1A, a gate dielectric layer 11 is formed on a substrate 10.
A polysilicon layer 12 is formed on the gate dielectric layer 11.
Ion implantation is performed on the polysilicon layer 12. N+ ions or P+ ions may be implanted depending upon whether the substrate 10 is an N-type or a P-type semiconductor.
As shown in FIG. 1B, a metal layer for an electrode is formed on the polysilicon layer 12. After forming a hard mask layer on the metal layer for an electrode, patterning is performed to form a gate pattern G in which a polysilicon electrode 12A, a metal electrode 13, and a gate hard mask 14 are stacked.
However, the above-described conventional method for fabricating a gate pattern raises concerns regarding dopant penetration and segregation phenomena, which result from insufficient doping of the polysilicon electrode 12A or continuous decrease in the thickness of the gate dielectric layer 11 according to the size decrease of semiconductor devices. Also, concerns are raised in that the on-current of the device is likely to be degraded due to poly depletion and the transconductance of the device is likely to be degraded due to increase in the effective thickness (Tox) of an oxide layer.
In addition, as the size of a semiconductor device decreases, the poly depletion effect resulting from overlapping gate edge fringing fields in short channels increases and contributes to degradation of device characteristics. Therefore, it is desired to alleviate such a gate edge fringing field crowding phenomenon.